TOMI™ Technology Implementations
Intellectual Property
Venray sells intellectual property that enables the production of disruptive products and services. From time to time we execute reference designs to highlight specific product benefits enabled by our IP.
TOMI CELESTE - 2012-2013
This effort takes us right to the edge of DRAM performance. The architecture is optimized for Big Data benchmarks and graph analytics in particular. Our parent memory is an 8-bank 4G commodity DRAM.
Features:
- 8-core 64-bit CPU
- Full 64-bit unified address space
- Integrated network controller (optimized for 3D Torus)
- Supported by gcc C, C++, Fortran, and rest of Linux toolchain
- 4G 8-bank DRAM
- Low-voltage differential addressing to 15 other Celeste chips
- Ultra-low power standby
- Six power saving modes
TOMI BOREALIS - 2011
Objectives:- Tune the architecture for massively parallel Big Data performance
- Optimize cache behavior
- Improve behavior with compiler optimizer
- 42nm 3-layer metal stack capacitor
- 1Gbyte DRAM as the parent memory
- 8-core 32-bit CPU, 16-bit instructions, and virtual memory controller
- Traditional 4K Data Cache and 4K Instruction Cache
- Supported by gcc C, C++, Fortran, ADA and rest of Linux toolchain
- 1G 8-bank DRAM
- 16-bit interface to PCIe controller
- Low-voltage differential addressing to 15 other Borealis chips
- 4-bit SDIO
- Four power saving modes
- 2.1Ghz CPU speed
- About 50% the clock-for-clock performance of a 64-bit INTEL Xeon running Big Data apps
- TOMI Borealis Big Data Benchmark vs. INTEL Xeon
- 98mw (milliwatts) per CPU at full speed
- Production cost: about $2.00
TOMI AURORA - 2010
Objectives:- Design and characterize a digital gate and analog function library from DRAM transistors.
- Design a 32-bit CPU that could be routed with only 3-layers of metal.
- Demonstrate that caches could be closely merged with DRAM sense amps.
- Do it all with standard unmodified DRAM processing and DRAM memory blocks.
- 110nm 3-layer metal stack capacitor
- 64Mbyte DRAM as the parent memory
- Digital Cells
- Analog Cells
- TOMI Aurora Detailed Specification
- 4-core 32-bit CPU, 8-bit instructions, and virtual memory controller
- Supported by gcc compiler
- 64M 4-bank DRAM
- 4G addressing DDR2 external memory controller
- 4-bit SDIO
- Dual LCD controller
- Single line 4096-bit cache associated with addressing registers
- Four power saving modes
- 500Mhz CPU speed
- About 70% the clock-for-clock performance of an ARM Cortex A
- 21mw (milliwatts) per CPU at full speed
- 600uw per CPU at 12Mhz reduced power mode
- 38sq mm
- 18,000 transistors/CPU
- Production cost: about $0.60
TOMI Borealis vs. Xeon E5620 System
TOMI Aurora, 5.6 x 6.7mm