Digital Cells Implemented Using DRAM Transistors
A kernel digital standard cell library is used to implement all digital blocks except those in the cpu. The cpu cells will use a similar set of functions but will be massaged to suit the space and the optimum drive.
The cells in the kernel library are listed below. In that table, the function is defined in Boolean terms where "^" indicates "AND, "v" indicates "OR", "#" indicate "NOT", "<>" indicates a tri-state function, and "+>" defines a latched function
Drive Strengths: 0X uses minimum sized devices with balanced delay (inverter) 1X is 3 ns/pF (approx) 2X is 1.5 ns/pF (approx) 3X is 1.0 ns/pF (approx) 4X is 0.75ns/pF (approx)
| Cell Name | Cell Function | Boolean Description | Drive Strength |
|---|---|---|---|
| AN2X0 | 2-input AND | Z=A^B | 0 |
| AN2X1 | 2-input AND | Z=A^B | 1 |
| AN3X0 | 3-input AND | Z=A^B | 0 |
| AN3X1 | 3-input AND | Z=A^B^C | 1 |
| AN4X0 | 4-input AND | Z=A^B^C^D | 0 |
| AN4X1 | 4-input AND | Z=A^B^C^D | 1 |
| AO21X1 | AND/OR | Z=(A^B)vC | 1 |
| AO22X1 | AND/OR | Z=(A^B)v(C^D) | 1 |
| BUFX0 | Non-inverting buffer | Z=A | 0 |
| BUFX1 | Non-inverting buffer | Z=A | 1 |
| BUFX4 | Non-inverting buffer | Z=A | 4 |
| BUFX8 | Non-inverting buffer | Z=A | 8 |
| BUFX12 | Non-inverting buffer | Z=A | 12 |
| BUFX16 | Non-inverting buffer | Z=A | 16 |
| DFFNRX1 | -ve edge triggered D-type with Reset | Q=>D^#R; QB=#DvR | 1 |
| DFFPRSX1 | +ve edge triggered D-type with Set and Reset | Q=>(D^#R)vS; QB=(#DvR)^#S | 1 |
| DFFPRX1 | +ve edge triggered D-type with Reset | Q=>D^#R; QB=#DvR | 1 |
| DFFPX1 | +ve edge triggered D-type | Q=>D; QB=D# | 1 |
| FADX1 | Full Adder | CO=(CI^(AvB))v(A^B); S=(#CO^(AvBvCI))v(AvBvCI) | 1 |
| GLATX1 | Gated D Latch | Q=#(#(D^EN)^#Q); QB=#(#(EN^#(D^EN))^Q) | 1 |
| HADX1 | Half-Adder, S=A+B, C=Carry | S=(AvB)^#(A^B), C=A^B | 0 |
| INVX0 | Inverter | Z=#A | 0 |
| INVX1 | Inverter | Z=#A | 1 |
| INVX2 | Inverter | Z=#A | 2 |
| INVX3 | Inverter | Z=#A | 3 |
| INVX4 | Inverter | Z=#A | 4 |
| INVX16 | Inverter | Z=#A | 16 |
| INVX24 | Inverter | Z=#A | 24 |
| ND2X0 | 2-input NAND | Z=#(A^B) | 0 |
| ND2X1 | 2-input NAND | Z=#(A^B) | 1 |
| ND2X2 | 2-input NAND | Z=#(A^B) | 2 |
| ND3X0 | 3-input NAND | Z=#((A^B)^C) | 0 |
| ND3X1 | 3-input NAND | Z=#((A^B)^C) | 1 |
| ND3X2 | 3-input NAND | Z=#((A^B)^C) | 2 |
| ND4X0 | 4-input NAND | Z=#((A^B)^(C^D)) | 0 |
| ND4X1 | 4-input NAND | Z=#((A^B)^(C^D)) | 1 |
| ND4X2 | 4-input NAND | Z=#((A^B)^(C^D)) | 2 |
| NR2X0 | 2-input NOR | Z=#(AvB) | 0 |
| NR2X1 | 2-input NOR | Z=#(AvB) | 1 |
| NR2X2 | 2-input NOR | Z=#(AvB) | 2 |
| NR3X0 | 3-input NOR | Z=#((AvB)vC) | 0 |
| NR3X1 | 3-input NOR | Z=#((AvB)vC) | 1 |
| NR3X2 | 3-input NOR | Z=#((AvB)vC) | 2 |
| NR4X0 | 4-input NOR | Z=#((AvB)v(CvD)) | 0 |
| NR4X1 | 4-input NOR | Z=#((AvB)v(CvD)) | 1 |
| OA24X1 | OR/NAND | Z=#(((A^B)^C^D))V((C^D)^(E^F))) | 1 |
| MUX2X1 | 2-input multiplexer | Z=(A^#SL) v (B^SL) | 1 |
| SBRBLATX1 | #S, #R latch | Q=#(SB^QB); QB=#(RB^Q) | 1 |
| SRLATX1 | SR Latch | Q=#(R^QB); QB=#(S^Q) | 1 |
| TIEHILOX1 | Logic High and Low | HI=TRUE, LO=FALSE | 1 |
| TRINIX1 | Tristate Buffer with enable and enable bar | Z<>A | 1 |
| TRINIX2 | Tristate Buffer with enable and enable bar | Z<>A | 2 |
| TRIX0 | Tristate Inverter with enable | Z<>#A | 0 |
| TRIX1 | Tristate Inverter with enable | Z<>#A | 1 |
| TRIX2 | Tristate Inverter with enable | Z<>#A | 2 |
| TRIX2B | Tristate Inverter with enable and enable bar | Z<>#A | 2 |
| TRIXOR3AX1 | Tristate 3-input exclusive NOR (AB, B, C inputs) | Z<>(#AB^#B^#C)v(B^AB^#C)v(C^AB^#B)v(#AB^B^C) | 1 |
| TRIXOR3X1 | Tristate 3-input exclusive NOR (A, B, C inputs) | Z<>(A^#B^#C)v(B^#A^#C)v(C^#A^#B)v(A^B^C) | 1 |
| XNOR2X1 | 2-input exclusive NOR | Z=#((AVB)^#(A^B)) | 1 |
| XOR2X1 | 2-input Exclusive OR | Z=(AVB)^#(A^B) | 1 |
| XOR3X1 | 3-input exclusive NOR | Z=(A^#B^#C)v(B^#A^#C)v(C^#A^#B)v(A^B^C) | 1 |