TOMI Technology Intellectual Property For Sale
What It Is
TOMI Technology enables CPU cores within commodity DRAM dies using existing DRAM transistors and unmodified DRAM processes.
As a result of the proximity of its CPUs to main memory, TOMI solves two of the three limitations on computer improvement:
- The Power Wall and
- The Memory Wall.
Furthermore, by fabricating CPU cores using DRAM transistors, TOMI reduces the cost of microprocessor cores by nearly a factor of 100.
The Enabling Technology
Engineers have attempted to merge CPU and main memory for nearly 3 decades. Most previous attempts were not commercially viable due to the performance compromises and high cost of embeddeding DRAM onto CPU logic.
The solution requires performing the opposite, embedding CPU logic in the DRAM. Such merging required the invention of the following enabling technologies:
A CPU small enough to connect using the 3-layers of metal on DRAM processes.
The Minimum Instruction Set TOMI CPU requires only 22,000 transistors yet benchmarks favorably against legacy architectures many times its size.
A cache architecture that matches the tight physical pitch of most DRAM sense amps.
TOMI caches achieve high speed, low power, and high packing density while still routing with only 3-layers of metal.
A low voltage bus architecture that hooks everything together at high speed but very low power.
What Is It Good For
TOMI Technology is optimized for the two computer challenges of the next decade:
What the Acquirer Gets
- A Minimum Instruction Set CPU for Embedding in Commodity DRAM
- Monolithic Cache Loads in Single Memory Cycle
- Efficient Cache Management System for Merged Memory-CPU Architectures
- A Means of Reducing Power of High Speed Monolythic Busses
- A Means of Parallelizing Cache Access and CPU Execution
- A Means of Implementing Memory Hierarchy Interprocessor Communications
- A Means of Very Low Power Standby Execution Using Monolythic Caches
- A Means of Booting Merged Memory-CPU Architectures
- A High Speed Least Frequently Used Detector
Implementations and Software
- USPTO Patent Application US2007/0192568 A1, (TOMI I) filed August 16, 2007
- Australia Application No. 2007212342
- European Patent Application No. 07763540.7, Patent No. 1979808
--- Germany (602007019211.0)
--- United Kingdom
- Japan Patent Application No. 2008-553428, Patent No. 4987882
- Korea Patent No. 1120398
- Russia Patent No. 2427895
- USPTO Patent Application US2008/0320277 A1, (TOMI II) filed December 25, 2008
Related PCT pending in:
- United Kingdom
- Australia Divisional Application No. 2008355072
- Korea Patent No. 1121606
- Russia Patent No. 2450339
- USPTO Patent Application Serial No. 12/965,885, CPU in Memory Cache Architecture, filed December 12, 2011
- Digital Library implemented using DRAM transistors, 60+ cells
- Analog library implemented using DRAM transistors, low noise amp, pll, A/D, sdr, etc.
- TOMI Aurora logic files, layout files, test vectors, LVS'd and DRC'd
- TOMI Aurora benchmarks, image rendering, video, Hidden Markov Model, etc.
- TOMI Aurora Shirtbook design and schematic
- Linux toolchain: linker, loader, assembler, simulator, debugger, including TOMI optimized gcc: C, C++, Fortran
- TOMI Borealis cache design study
- Massively Parallel 16K-core 256GB motherboard design
- TOMI Borealis logic files, test vectors
- Interprocessor bus SPICE design study
- On-chip SDIO bootloader
- Access to and use of TOMI CPU architects, chip designers, layout technicians, and programmers (some limitations apply)
"I actually have to go on record as saying that, at some time, this (TOMI) would be the way to go."
- Dr. David Patterson (RISC visionary, SPARC inventor, IRAM inventor)
"...delighted, even envious" WIRED
- Dr. Thomas Sterling (Creator of Beowolf supercomputer, DARPA Excascale project, Gilgamesh inventor)
"The entity that controls [TOMI] probably controls computer architecture to the end of silicon." WIRED
- Russell Fish