TOMI Technology enables CPU cores within commodity DRAM dies using existing DRAM transistors and unmodified DRAM processes.
As a result of the proximity of its CPUs to main memory, TOMI solves two of the three limitations on computer improvement:
Furthermore, by fabricating CPU cores using DRAM transistors, TOMI reduces the cost of microprocessor cores by nearly a factor of 100.
Engineers have attempted to merge CPU and main memory for nearly 3 decades. Most previous attempts were not commercially viable due to the performance compromises and high cost of embeddeding DRAM onto CPU logic.
The solution requires performing the opposite, embedding CPU logic in the DRAM. Such merging required the invention of the following enabling technologies:
A CPU small enough to connect using the 3-layers of metal on DRAM processes.
The Minimum Instruction Set TOMI CPU requires only 22,000 transistors yet benchmarks favorably against legacy architectures many times its size.
A cache architecture that matches the tight physical pitch of most DRAM sense amps.
TOMI caches achieve high speed, low power, and high packing density while still routing with only 3-layers of metal.
A low voltage bus architecture that hooks everything together at high speed but very low power.
TOMI Technology is optimized for the two computer challenges of the next decade:
Massively Parallel Big Data Distributed Servers
Very Low Power Yet High Performance Portable Communicating Computing Appliances
"I actually have to go on record as saying that, at some time, this (TOMI) would be the way to go." EDN
- Dr. David Patterson (RISC visionary, SPARC inventor, IRAM inventor)
"...delighted, even envious" WIRED
- Dr. Thomas Sterling (Creator of Beowolf supercomputer, DARPA Excascale project, Gilgamesh inventor)
"The entity that controls [TOMI] probably controls computer architecture to the end of silicon." WIRED
- Russell Fish